`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    18:32:21 11/13/2011 
// Design Name: 
// Module Name:    exerciser 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module PcieAxiBridgeDevice(
  input           CLK,
  input           RST,

  input   [31:0]  S_AWADDR,
  input           S_AWVALID,
  output          S_AWREADY,
  input   [31:0]  S_WDATA,
  input   [3:0]   S_WSTRB,
  input           S_WVALID,
  output          S_WREADY,
  output  [1:0]   S_BRESP,
  output          S_BVALID,
  input           S_BREADY,
  input   [31:0]  S_ARADDR,
  input           S_ARVALID,
  output          S_ARREADY,
  output  [31:0]  S_RDATA,
  output  [1:0]   S_RRESP,
  output          S_RVALID,
  input           S_RREADY,

  input           S_TVALID,
  output          S_TREADY,
  input   [127:0] S_TDATA,
  input   [3:0]   S_TSTRB,
  input   [47:0]  S_TUSER,
  input           S_TLAST,

  output          M_TVALID,
  input           M_TREADY,
  output  [127:0] M_TDATA,
  output  [3:0]   M_TSTRB,
  output  [47:0]  M_TUSER,
  output          M_TLAST,

  input   [31:0]  S0_AWADDR,
  input   [7:0]   S0_AWLEN,
  input           S0_AWVALID,
  output          S0_AWREADY,
  input   [31:0]  S0_WDATA,
  input   [3:0]   S0_WSTRB,
  input           S0_WVALID,
  output          S0_WREADY,
  output  [1:0]   S0_BRESP,
  output          S0_BVALID,
  input           S0_BREADY,
  input   [31:0]  S0_ARADDR,
  input   [7:0]   S0_ARLEN,
  input           S0_ARVALID,
  output          S0_ARREADY,
  output  [31:0]  S0_RDATA,
  output  [1:0]   S0_RRESP,
  output          S0_RVALID,
  input           S0_RREADY,

  output  [31:0]  M0_AWADDR,
  output  [7:0]   M0_AWLEN,
  output          M0_AWVALID,
  input           M0_AWREADY,
  output  [31:0]  M0_WDATA,
  output  [3:0]   M0_WSTRB,
  output          M0_WLAST,
  output          M0_WVALID,
  input           M0_WREADY,
  input   [1:0]   M0_BRESP,
  input           M0_BVALID,
  output          M0_BREADY,
  output  [31:0]  M0_ARADDR,
  output  [7:0]   M0_ARLEN,
  output          M0_ARVALID,
  input           M0_ARREADY,
  input   [31:0]  M0_RDATA,
  input           M0_RLAST,
  input   [1:0]   M0_RRESP,
  input           M0_RVALID,
  output          M0_RREADY
  );

  wire          pab_s_tvalid;
  wire          pab_s_tready;
  wire [127:0]  pab_s_tdata;
  wire [3:0]    pab_s_tstrb;
  wire          pab_s_tlast;
  wire          pab_m_tvalid;
  wire          pab_m_tready;
  wire [127:0]  pab_m_tdata;
  wire [3:0]    pab_m_tstrb;
  wire          pab_m_tlast;

  InternalDevice 
  idev(
    .CLK            (CLK     ),
    .RST            (RST     ),

    .M_PRI_TVALID   (M_TVALID),
    .M_PRI_TREADY   (M_TREADY),
    .M_PRI_TDATA    (M_TDATA ),
    .M_PRI_TSTRB    (M_TSTRB ),
    .M_PRI_TLAST    (M_TLAST ),
    .S_PRI_TVALID   (S_TVALID),
    .S_PRI_TREADY   (S_TREADY),
    .S_PRI_TDATA    (S_TDATA ),
    .S_PRI_TSTRB    (S_TSTRB ),
    .S_PRI_TLAST    (S_TLAST ),

    .M_SEC_TVALID   (pab_s_tvalid),
    .M_SEC_TREADY   (pab_s_tready),
    .M_SEC_TDATA    (pab_s_tdata),
    .M_SEC_TSTRB    (pab_s_tstrb),
    .M_SEC_TLAST    (pab_s_tlast),
    .S_SEC_TVALID   (pab_m_tvalid),
    .S_SEC_TREADY   (pab_m_tready),
    .S_SEC_TDATA    (pab_m_tdata),
    .S_SEC_TSTRB    (pab_m_tstrb),
    .S_SEC_TLAST    (pab_m_tstrb)
  );

  pcie_axi_bridge 
  pab(
    .CLK            (CLK      ),
    .RST            (RST      ),

    .S_AWADDR       (S_AWADDR ),
    .S_AWVALID      (S_AWVALID),
    .S_AWREADY      (S_AWREADY),
    .S_WDATA        (S_WDATA  ),
    .S_WSTRB        (S_WSTRB  ),
    .S_WVALID       (S_WVALID ),
    .S_WREADY       (S_WREADY ),
    .S_BRESP        (S_BRESP  ),
    .S_BVALID       (S_BVALID ),
    .S_BREADY       (S_BREADY ),
    .S_ARADDR       (S_ARADDR ),
    .S_ARVALID      (S_ARVALID),
    .S_ARREADY      (S_ARREADY),
    .S_RDATA        (S_RDATA  ),
    .S_RRESP        (S_RRESP  ),
    .S_RVALID       (S_RVALID ),
    .S_RREADY       (S_RREADY ),

    .S_TVALID       (pab_s_tvalid),
    .S_TREADY       (pab_s_tready),
    .S_TDATA        (pab_s_tdata),
    .S_TSTRB        (pab_s_tstrb),
    .S_TLAST        (pab_s_tlast),
    .M_TVALID       (pab_m_tvalid),
    .M_TREADY       (pab_m_tready),
    .M_TDATA        (pab_m_tdata),
    .M_TSTRB        (pab_m_tstrb),
    .M_TLAST        (pab_m_tlast),

    .S0_AWADDR       (S0_AWADDR ),
    .S0_AWVALID      (S0_AWVALID),
    .S0_AWREADY      (S0_AWREADY),
    .S0_WDATA        (S0_WDATA  ),
    .S0_WSTRB        (S0_WSTRB  ),
    .S0_WVALID       (S0_WVALID ),
    .S0_WREADY       (S0_WREADY ),
    .S0_BRESP        (S0_BRESP  ),
    .S0_BVALID       (S0_BVALID ),
    .S0_BREADY       (S0_BREADY ),
    .S0_ARADDR       (S0_ARADDR ),
    .S0_ARVALID      (S0_ARVALID),
    .S0_ARREADY      (S0_ARREADY),
    .S0_RDATA        (S0_RDATA  ),
    .S0_RRESP        (S0_RRESP  ),
    .S0_RVALID       (S0_RVALID ),
    .S0_RREADY       (S0_RREADY ),
  
    .M0_AWADDR       (M0_AWADDR ),
    .M0_AWLEN        (M0_AWLEN  ),
    .M0_AWVALID      (M0_AWVALID),
    .M0_AWREADY      (M0_AWREADY),
    .M0_WDATA        (M0_WDATA  ),
    .M0_WSTRB        (M0_WSTRB  ),
    .M0_WLAST        (M0_WLAST  ),
    .M0_WVALID       (M0_WVALID ),
    .M0_WREADY       (M0_WREADY ),
    .M0_BRESP        (M0_BRESP  ),
    .M0_BVALID       (M0_BVALID ),
    .M0_BREADY       (M0_BREADY ),
    .M0_ARADDR       (M0_ARADDR ),
    .M0_ARLEN        (M0_ARLEN  ),
    .M0_ARVALID      (M0_ARVALID),
    .M0_ARREADY      (M0_ARREADY),
    .M0_RDATA        (M0_RDATA  ),
    .M0_RRESP        (M0_RRESP  ),
    .M0_RLAST        (M0_RLAST  ),
    .M0_RVALID       (M0_RVALID ),
    .M0_RREADY       (M0_RREADY )
  );

endmodule
